Prior art routing schemes such as those based on a geometric matching algorithm r a weighted center algorithm strive to equalize a respective delay to each of a plurality of points. Such equalized delay is advantageous for minimizing skew of a signal reaching each point.
FIG. 1A shows an integrated circuit 102 with a plurality of points P1, P2, P3, and P4 to receive a common signal such as a clock signal for example. Such points P1, P2, P3, and P4 indicate locations of nodes of the integrated circuit 102 inputting the common clock signal.
Referring to FIG. 1B, in the geometric matching algorithm, a first segment 104 is drawn between two nearest points P1 and P2, and a second segment 106 is drawn between two nearest points P3 and P4. In addition, a third segment 108 is drawn between the mid-points of the segments 104 and 106.
Such segments 104, 106, and 108 indicate wiring between the points P1, P2, P3, and P4. The common signal is tapped into a point 110 along the third segment 108 to result in equal delay from such a point 110 to each of the points P1, P2, P3, and P4. For example, if the length of the segments 104 and 106 are equal, then the point 110 is the mid-point of the segment 108. Otherwise, the location of the point 110 is adjusted along the length of the segment 110 until the distance from the point 110 along the segment 110 and one of the segments 104 and 106 is equal for each of the points P1, P2, P3, and P4.
As a result, if the common signal is input at the point 110, the common signal reaches each of the points P1, P2, P3, and P4 with equalized delay and thus with minimized skew. The prior art routing schemes such as the geometric matching algorithm or the weighted center algorithm strive to equalize the wiring distance to the points of the integrated circuit, but do not strive to minimize the wiring length to the points of the integrated circuit. However, in some integrated circuits, minimizing the wiring length may be important. For example, minimizing the wiring length may be important for minimizing area, complexity, and signal delay of the integrated circuit.